A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

摘要

A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locke