High-speed dynamic CMOS latch, flip-flop, and frequency divider circuits

摘要

A high-speed dynamic CMOS flip-flop comprises two cascaded dynamic latches and an output circuit P5 ,N5. Each of the latches comprises a CMOS transistor pair N1 P1 or P3,N3 with an interposed clocked transmission gate P2,N2 or P4,N4. Use of the transmission gates in place of a single transistor (figure 1) allows the dynamic storage nodes 001-004 to be charged and discharged rapidly and symmetrically to good logic levels. This permits an improved output waveform, and allows a higher operating frequency or lower operating current at a given frequency. The flip-flop may be used to divide the frequency of the clock signal CLK,CLKB by connecting the output QB to the input DATA.