A New High-Speed Multiplier Using Modified Partial Product Reduction Algorithm

摘要

In This paper a new high-speed multiplier using modified partial product reduction algorithm with Wallace method is proposed. Three important modifications are done for multiplier in this study. In partial product generation step of multiplication a new Booth algorithm is proposed which decreases number of partial products quarterly. In partial product reduction method a modified Wallace algorithm is presented that sums partial products very fast and is more regular than previous works. In final addition step a novel final adder are presented that sums two final operands efficiently. Simulations are done using HSPICE in 80 nm CMOS technology. Presented multiplier decreases number of transistors more than 14 percent, power consumption reduction is 16 percent and area reduction is 8 percent in compare with previous works.