Digital multiplier based upon a regularly structured sum of products adder array for partial product reduction

摘要

A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.