Analysis and design of dynamic current mode logic circuits for high-speed adders and array multipliers.

摘要

This thesis is about the analysis and design of Dynamic Current Mode Logic (DyCML) circuits for high-speed adders and multipliers. To achieve high performance at a low-supply voltage with low-power dissipation, a reduced swing logic style called DyCML is introduced. Several logic styles, involving conventional static logic styles such as Complementary Metal Oxide Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL) and dynamic logic styles such as Domino, MOS Current Mode Logic (MCML) and the proposed DyCML are analyzed at both the gate and block levels. High-speed 16-bit adders like Conditional Carry Select, Successively Incremented Carry Number Block, Carry Look-Ahead and Brent Kung adders as well as the 8-bit Array Multiplier are designed using each of the above mentioned logic design styles and their power dissipation and speed are evaluated by using PSPICE simulations of a 0.5μm CMOS technology and the results of these tests are reported for comparison purposes.