A method for reducing the area of a multiplier, generating a partial product for high-speed operation, and implementing a partial product adder tree

摘要

1. The technical field to which the invention described in the claims belongs;How to multiply floating point data.;2. Technical Problems to be Solved by the Invention;In this paper, we propose a method to reduce the area of multiplier with large area using many hardware, generate partial product using Boolean algorithm to improve operation speed, and construct additive tree using special modules.;3. The point of the solution of the invention;Basically, the Boolean algorithm is used to generate partial products, special modules that pass the upper and lower bits to reduce the area of the data path to the minimum, and use a half adder or full adder in the middle, And to provide a partial product generation method and a partial product addition tree implementation method that can reduce the consumed area.;4. Important Uses of the Invention;Used in all chip designs that require multiplication of floating point data.