首页> 外国专利> Multiply circuit and method that detects portions of operands whose partial products are superfluous and modifies partial product manipulation accordingly

Multiply circuit and method that detects portions of operands whose partial products are superfluous and modifies partial product manipulation accordingly

机译:检测部分乘积多余的操作数部分并相应修改部分乘积操作的乘法电路和方法

摘要

Multiplication circuitry performs a multiply operation to multiply a multiplicand operand and a multiplier operand to form a total product of the multiplication operation, where the multiplier operand includes a plurality of multiplier operand portions. The multiplication circuitry includes multiplier circuitry configured to multiply each of the multiplier operand portions and the multiplicand operand, in a sequence, to form a sequence of partial products corresponding to the sequence of multiplier operand portions. The multiplier circuitry further includes combining circuitry configured, for each multiplier operand portion, to combine the partial product corresponding to that multiplier operand portion with a previous partial result, to generate a new partial result corresponding to that multiplier operand portion. Detection circuitry is configured to determine, for each multiplier operand portion and based on that multiplier operand portion, if the new partial result corresponding to that multiplier operand portion would not affect the final result of the multiplication. For example, the detection circuitry may be specifically configured to determine whether the multiplier operand portion is all zeros or all ones. Control circuitry is configured to control operations of the combining circuitry responsive at least to the determination of the detection circuitry for that multiplier operand portion.
机译:乘法电路执行乘法运算以将被乘数操作数和乘法器操作数相乘以形成乘法运算的总积,其中乘法器操作数包括多个乘法器操作数部分。乘法电路包括乘法器电路,该乘法器电路被配置为按顺序将每个乘法器操作数部分和被乘数操作数相乘,以形成与乘法器操作数部分的序列相对应的部分乘积的序列。乘法器电路还包括组合电路,该组合电路被配置用于每个乘法器操作数部分,以将对应于该乘法器操作数部分的部分乘积与先前的局部结果组合,以生成对应于该乘法器操作数部分的新的局部结果。检测电路被配置为针对每个乘法器操作数部分并基于该乘法器操作数部分,确定与该乘法器操作数部分相对应的新的部分结果是否不会影响乘法的最终结果。例如,检测电路可以被具体地配置为确定乘法器操作数部分是全零还是全一。控制电路被配置为至少响应于该乘法器操作数部分的检测电路的确定来控制组合电路的操作。

著录项

  • 公开/公告号US6173303B1

    专利类型

  • 公开/公告日2001-01-09

    原文格式PDF

  • 申请/专利权人 NATIONAL SEMICONDUCTOR CORP.;

    申请/专利号US19980187204

  • 发明设计人 YORAM AVIGDOR;LIMOR LEVY;

    申请日1998-11-06

  • 分类号G06F75/20;G06F70/00;

  • 国家 US

  • 入库时间 2022-08-22 01:05:44

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