Area efficient error compensation circuit for fixed width unsigned multiplier by probabilistic analysis of partial product array

摘要

Currently DSP is applied in many areas of applications such as wireless communication, Image processing, speech processing etc. These areas demand fast and small size elements. Several arithmetic operations such as multiplications & additions are performed by DSP processors per output. Out of these multiplication plays a very important role. So system performance is directly related to multipliers. In this paper we are going to design a fixed width unsigned multiplier using probabilistic approach. The multiplier is first encoded in order to reduce partial product array & then fixed width multiplier is obtained. This introduces high error in final product. In order to reduce this error compensation is needed. In this paper for error compensation probability estimation of partial products are used. We also tried to reduce the area by minimizing the logic component in bias circuit.