Method and system for efficiently multiplying signed and unsigned variable width operands

摘要

A plurality of multipliers for multiplying numbers having B number of bits are provided for multiplying A-operands having B number of bits by a B-operand having B number of bits. Pairs of A- and B-operands are loaded into each multiplier. Each of the multipliers calculates an intermediate result by internally adding B number of partial products. In response to the data processing system being operated in a signed mode, selected bits in selected partial products in selected multipliers are complemented, and 2.sup.B is added to a selected intermediate result so that when the intermediate results are appropriately weighted and added together, a result that is the product of two operands having 2B- bits may be calculated. In another mode, multiple products having B-bits are calculated from the pairs of A- and B-operands. The A- and B- operands may be either signed or unsigned.