3D Chip Stack Technology Using Through-Chip Interconnects

摘要

THE CURRENT TECHNOLOGY in micro- and nano-electronics is insufficient to meet future demands for several applications. For instance, embedded applications for communication (such as mobile phones and PDAs) and driver assistance systems for automobiles require the reliable fusion of subsystems fabricated in mixed technologies (sensors, actuators, analog, or memory) and low-power high-performance processing capabilities. Here, most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. Furthermore, global buses, which are necessary to connect subsystems arranged on a two-dimensional chip area, limit performance and power consumption. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Here, the designer builds a system by stacking several dies. Using an optimized standard technology (CMOS or sensor, for example), a manufacturer fabricates each layer of this chip stack, implementing additional processing steps to prepare the individual dies for the stacking process. Interchip connections, which compose a 2D arrangement on both the front and back sides of the stacked dies, create electrical connections. Interchip vias provide connectivity between arbitrary layers of the physical architecture, resulting in short connection lengths, which enhance performance and decrease power consumption significantly.