A distributed VLSI architecture for efficient signal and data processing

摘要

Future signal and data processing applications will require billions of operations per second, and yet low hardware and software development costs. Architectural improvements in the form of multiprocessors must be used in order to reach these high performance levels. Von Neumann models cannot easily implement concurrent operations and data-flow principles are one alternative for sequencing instructions in a parallel environment. The machine described here, the Hughes Data-Flow Multiprocessor (HDFM), is a high-performance, scalable, fault-tolerant, highly programmable multicomputer designed for embedded signal and data processing applications. The architecture of the machine is described in detail, and the influence on the final design of various requirements such as weight, size, power consumption, performance level, and reliability are shown. The processing elements have been designed so as to reduce the number of VLSI component types required and for modularity of the physical system. The modular nature of the architecture allows a range of throughput and reliability requirements to be met. The model of execution derived from original data-flow principles is presented as well as the different software tools which give the system its high-level language pro-grammability (compiler, allocator, etc.). Complex constructs (such as large structure handling) are demonstrated. Finally, the results of a deterministic simulation of the machine show that a 64 processing element machine may provide real throughput of 64 million instructions per second (MIPS).