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首页> 外文期刊>Components, Packaging and Manufacturing Technology, IEEE Transactions on >Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration
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Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration

机译:用于细间距(≤10μm)的硅互连织物异构整合

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摘要

The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings (<= 50 mu m) using fine-pitch (<= 10 mu m) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal-metal [copper-copper (Cu-Cu)] thermal compression bonding was developed. Using this process, sub-10-mu m-pitch interconnects with a low specific contact resistance of <= 0.7 Omega.gm(2) and high shear force of 90 N for 4-mm(2) dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links (<= 500 mu m) with low loss (<= 2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<20 ps), low energy per bit (<= 0.03 pJ/b), and high data rates (up to 10 Gh/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4-23x higher data bandwidth, 3-65x lower latency, and 5-40x lower energy per bit compared to existing integration schemes.
机译:积极的摩尔人类律缩放的明显饱和度是通过传统包装和集成方案推动传统包装和集成方案的界限,以适应不断增长的数据带宽和异质性需求。在本文中,我们将硅互连面料(SI-IF)技术作为传统印刷电路板(PCB)的优越替代方案,以增强系统缩放。 Si-If是一种基于硅,包装的较小,高度可扩展的异构集成平台,可以组装和集成大规模晶片级系统。在该技术中,使用微距(<=10μm)管芯 - 基板互连在小型间距间距(<=50μm)的小型间距(<=50μm),允许在系统级别紧密集成的情况下,在Si-IF上紧密组装包裹。为了实现这些细间距互连,开发了一种新的组装技术,使用焊料直接金属 - 金属ε进行热压缩粘合。使用该方法,成功地证明了具有低特异性接触电阻的低比接触电阻的亚10-mu m间距互连和40n的高剪切力为4mm(2)芯管芯。此外,这些细间距互连与小型间隔相结合,提供了大量并行短链路(<=500μm),其用于与片上连接相当的用于互通的interdiele通信的低损耗(<= 2 dB)。因此,简单的缓冲器可以使用用于在低链路等待时间芯片(SuperCHIPS)协议(<20个PS),低能量的每比特一个简单的通用并行接口管芯之间传输数据(<= 0.03 PJ / b)和高数据速率(高达到10 gh / s / link),对应于聚合数据带宽,最多为8 tb / s / mm。与现有的集成方案相比,超级芯片界面的优势在通过SI-IF上显示4-23x更高的数据带宽,3-65倍降低,5-40倍降低的能量。

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