Parallel and pipelined implementations of injected numeratorlattice digital filters

摘要

Parallel and pipelined implementations are effective measures fornimproving the maximum permissible sampling rate of a digital filter ifnall the data required by the arithmetic units are immediately availablenon demand. This implies that parallel access to the data should benpossible and that for any loop in the signal flow graph the total numbernof series delay elements should be at least equal to the total number ofnpipelined stages in that loop. In the conventional lattice form IIRndigital filter, the feedback loops are single-delay loops. As anconsequence, the conventional lattice form IIR filter does not benefitnsignificantly from parallel and pipelined implementation scheme. In thisnpaper, we introduce a new lattice form IIR filter structure where thennumber of delay elements in the loops can be set arbitrarily. Thisnrenders the new lattice form IIR filter amenable to parallel andnpipelined implementation