Improved two-step clock-feedthrough compensation technique forswitched-current circuits

摘要

A new clock-feedthrough compensation scheme for switched-currentncircuits is proposed. The scheme is especially suited for the design ofndelay lines for high-frequency operation. The circuit operates by usingnan improved two-step technique, in which the input is sampled in anparallel combination of a coarse and a fine memory transistor. Sincenboth transistors are of the same type, large switching transientsncompared to the conventional S2I scheme can be avoided. Usingnthe proposed circuit, the coarse memory has considerably more time tonsettle. Compared to the simple cell, the circuit solution requires onlynone extra switch and one additional clock phase