An analytical model for current, delay, and power analysis ofsubmicron CMOS logic circuits

摘要

An analytical model for computing the supply current, delay, andnpower of a submicron CMOS inverter is presented. A modified version ofnthe nth power law MOSFET model is proposed and used to relate thenterminal voltages to the drain current in submicron transistors. Bynfirst computing definable reference points on the output voltagenwaveform, and then using linear approximations through these points tonfind the actual points of interest, the desired speed and accuracy ofnthe inverter model are achieved. The most important part of the analysisnis a three-step approach for computing the time and output voltage whennthe short-circuit transistor changes its mode of operation. The time andnoutput voltage when the charging/discharging current reaches its maximumnare also calculated and then used to evaluate the propagation delay andncharacterize the output voltage waveform. The model has been validatednfor both 0.8 Μm (5 V) and 0.25 Μm (2.5 V) CMOS technologies, for anwide range of inverter sizes, input transition times, and capacitivenloads. It predicts the delay, peak supply current, and power dissipationnto within a few percent of HSPICE or ELDO simulations based on accuratenphysically based MOSFET models, while offering about two orders ofnmagnitude gain in CPU time based on a MATLAB implementation