Clocked very large scale CMOS digital circuit - uses delay circuits to generate varying delayed clock pulses to drive sub-circuits, thus reducing switching current surges

摘要

The CMOS digital circuit, is used in pipelining techniques for increasing data flow rate. The circuit is subdivided into smaller circuits (1,2...n), each of which are driven by separate four phase clocks (CLK4). The clocks are driven by pulses from a master clock which have been delayed by time increments (delta t, 2delta t,...n delta t). Synchronisation circuits control the data flow between the smaller circuits (1,2,...n), the data flow rate being determined by the clock frequency. USE/ADVANTAGE - Digital filter in Radio Link Pipelining Systems. Reduces size of current spikes, reducing power supply requirements.