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Low-voltage analog circuit design based on biased inverting opampconfiguration

机译:基于偏置反相运算放大器配置的低压模拟电路设计

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Analog circuit designs that use inverting opamp configuration cannbe converted into low-voltage designs by biasing the opamp inputncommon-mode voltage to near one of the supply rails. This is achieved bynintroducing a current source or a resistor between the opamp negativeninput terminal and one of the supply rails. Hence, in this technique,nopamps with limited input common-mode range can be used. In addition,nswitches can be incorporated in these circuits to allow a wide range ofnapplications. This technique also allows large input and output signalnswings (close to rail-to-rail), even at a very low-voltage supply. Tondemonstrate the proposed technique, four track-and-hold amplifiersn(THA's) and a 10 bit digital-to-analog converter (DAC) have beenndesigned in a conventional 1.2 Μm CMOS process and tested at a 1 Vnsupply. The DAC consumes less than 0.45 mW and has a maximum throughputnof 1 MS/s, with close to rail-to-rail output (0.1-0.9 V). The maximumndifferential nonlinearity error and integral nonlinearity error werenmeasured to be 1.7 least significant bits (LSB's) and 3.0 LSB's,nrespectively. Each THA dissipates less than 0.35 mW and achieves a holdnmode total harmonic distortion of less than -61 dB for a 100 kHz, 1.4 Vnp-p differential input signal, sampled at a rate of 1 MS/s
机译:通过将运算放大器输入非共模电压偏置到电源轨之一附近,无法将使用反相运算放大器配置的模拟电路设计转换为低压设计。这是通过在运算放大器负输入端子和电源轨之一之间引入电流源或电阻器来实现的。因此,在该技术中,可以使用输入共模范围有限的Nopamp。此外,n个开关可以集成在这些电路中,以实现广泛的应用。即使在非常低的电压电源下,该技术也允许较大的输入和输出信号摆幅(接近轨到轨)。为了证明所提出的技术,已经在传统的1.2μmCMOS工艺中设计了四个采样保持放大器n(THA)和一个10位的数模转换器(DAC),并在1 Vnsupply下进行了测试。 DAC的功耗不到0.45 mW,最大吞吐速率为1 MS / s,接近轨至轨输出(0.1-0.9 V)。最大微分非线性误差和积分非线性误差分别测量为1.7最低有效位(LSB)和3.0 LSB。对于100 kHz,1.4 Vnp-p差分输入信号,以1 MS / s的速率采样,每个THA的耗散均小于0.35 mW,并实现Holdnmode总谐波失真小于-61 dB

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