A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS

摘要

A new concept of floating-point-number representation is implemented in a time-to-digital converter (TDC), which adaptively scales its resolution according to the amount of input difference. With a fixed 6-bit significand number, the TDC provides five cases of the exponent (x1, x2, x4, x8, and x16) to indicate the scale information. A digital phase-locked loop (PLL) with the TDC is implemented in a 0.18-$mu hbox{m}$ CMOS. The TDC shows the minimum resolution of 3 ps with a total conversion range of 3.5 ns, the maximum operating frequency of 80 MHz, and the power consumption of 18 mW at 75 MHz. The PLL shows a lock range of 0.9–1.25 GHz and a root-mean-square jitter of 3.5 ps at 1.2 GHz.