A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

摘要

A 86 MHz–12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse–fine TDC and a 6–12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 ${hbox {mm}}^{2}$ synthesizer, which is appropriate for use in a Software-Defined Radio, features $DeltaSigma$ noise cancellation and digital phase modulation and consumes less than 30 mW.