Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter

摘要

An open-loop fractional divider is proposed to eliminate the deterministic jitter caused by the conventional fractional dividers without additional calibration. The proposed divider utilizes a new voltage-comparator-based digital-to-time converter (DTC) as an adjustable delay circuit to control the edges of the output clock of the divider. The proposed DTC proves to be power efficient considering its resolution and the frequency of the output clock. Detailed analysis of non-idealities of the proposed architecture and its effect on the cancellation of the deterministic jitter are presented and verified by simulations. Simulation results show that for an input frequency of 5.325 GHz and an output frequency of 1 GHz, the proposed divider achieves 0.2 ps of time resolution using a 10-bit DTC while consuming 3.72 and 1.17 mW from 1.2- and 0.9-V supply for 130- and 65-nm CMOS technology nodes, respectively.