Parametric Testing of HYPRES Superconducting Integrated Circuit Fabrication Processes

摘要

A set of diagnostic chips for process control and design parameters evaluation has been developed for HYPRES'' 1.0 ${rm kA/cm}^{2}$ , 4.5 ${rm kA/cm}^{2}$, and 20 ${rm kA/cm}^{2}$ fabrication processes, consisting of four 5 $times$ 5-mm chips. Testing was performed on automated test setup (OCTOPUX) that automatically logs results and maintains records of fabrication process and design parameters. The design of diagnostic structures and automated testing algorithms are discussed. Statistical data are presented on the uniformity and run-to-run variation of the critical currents, critical current density, junction size, inductances, and other fabrication and design parameters collected since September 2005. The influence of the fabrication parameters deviation on operational margins and yield of large superconducting digital integrated circuits is discussed, as well as requirements for the 20 ${rm kA/cm}^{2}$ (80 GHz) process.