机译:Au和Pd接触MoS_2的肖特基势垒高度
Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;
Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;
Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;
Department of Condensed Matter Physics and Materials Science, Tata Institute of Fundamental Research,Mumbai 400005, India;
Department of Condensed Matter Physics and Materials Science, Tata Institute of Fundamental Research,Mumbai 400005, India;
Department of Condensed Matter Physics and Materials Science, Tata Institute of Fundamental Research,Mumbai 400005, India;
Center of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India;
机译:Au和Pd接触MoS
机译:通过化学预处理在Au / III-V半导体肖特基势垒接触中引入的势垒高度不均匀性的弹道电子发射显微镜研究
机译:通过电流-电压(Ⅰ-Ⅴ)特性和深能级瞬态光谱研究Au / n-Hg_3In_2Te_6肖特基接触的势垒高度和陷阱中心
机译:Al,Ti,Au和Ni触点的肖特基势垒高度评估3C-SIC
机译:介电偶极子减轻了肖特基势垒高度调整,从而降低了接触电阻。
机译:硼铝双重注入与微波退火相结合对NiSi / Si接触处肖特基势垒高度的调节
机译:阻挡层高度对ZnO肖特基接触温度的依赖性