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Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

机译:利用双通道AlN / GaN高电子迁移率晶体管架构抑制表面起源的栅极滞后

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摘要

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f_t/f_(max) of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f_t/f_(max) of 48/60 GHz.
机译:展示了一种双通道AlN / GaN高电子迁移率晶体管(HEMT)结构,该结构利用超薄外延层来抑制与表面相关的栅极滞后。在AlN / GaN / AlN / GaN异质结构中使用了两个高密度二维电子气(2DEG)通道,其中顶部2DEG用作准等电位,用于屏蔽由分布的表面和界面态引起的电位波动。底部通道用作晶体管的调制通道。通过分子束外延在独立的氢化物气相外延GaN衬底上生长双通道AlN / GaN异质结构。用300 nm长的凹入式栅极制造的HEMT的栅极滞后比(GLR)为0.88,在低于阈值的偏压力下,漏极电流没有降低。这些结构还实现了27/46 GHz的小信号指标f_t / f_(max)。这些性能结果与具有0.74的GLR和82 mA / mm的电流塌陷,f_t / f_(max)为48/60 GHz的非嵌入式栅双通道HEMT形成对比。

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  • 来源
    《Applied Physics Letters》 |2016年第6期|063504.1-063504.5|共5页
  • 作者单位

    Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375, USA,Seagate Technology,Read Head Operations, Bloomington, Minnesota 55435, USA;

    Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375, USA;

    Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375, USA;

    Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375, USA;

    Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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