Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

摘要

The effects of precleaning processes by O(3)and SC-1 in depositing high-kappa gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O(3)cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.