A novel process to fabricate capacitive accelerometers integrated with Au/Si galvanic cell protection and antifuse on SoI wafer is presented and realized. The process employs the device layer of SoI wafers to shape the beam and the surface electrode, while micromachining the handle layer to form the mass plate. The release hole is formed by DRIE etching from the front side,and then to release the mass plate by TMAH etching,meanwhile, the beam and the surface electrode are protected by Au/Si galvanic cell. Being off-state before TMAH etching,the antifuse is broken through to on-state after TMAH etching. The silicon is passivated when the area ratio of gold and silicon is more than 5:1 by measuring the polarization curve of gold and silicon in 60 ℃ 25 % TMAH. The capacitive accelerometer structure is successfully fabricated, the range of unreleased and released beam width is 9.4-10 μm which indicates that the Au/Si galvanic cell protection is realized. Two breakdown antifuses in parallel have 5 ～25 kΩ on-state resistance.%提出并实现了一种利用SoI结合金硅原电池保护和反熔丝制作电容式加速度计的新工艺方法.该工艺用Sol顶层硅制作梁和上电极,用衬底制作质量块.采用DRIE从正面刻蚀形成释放孔,TMAH腐蚀实现质量块的释放,在TMAH腐蚀过程中利用金硅原电池保护实现梁和表面极板的保护.在TMAH腐蚀完成前,反镕丝保持断开状态,腐蚀完成后,击穿反镕丝形成导通状态.通过测量金和硅的极化曲线得到60℃25％ TMAH中实现原电池保护的金硅面积比不小于5∶1.成功制作成电容式加速度计结构,释放前后梁宽度均在9.4 ～10μm范围内,表明原电池保护有效.击穿后反熔丝并联导通电阻为5～25 kΩ之间.
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