基于FPGA的通用异步收发器设计

摘要

采用Verilog HDL语言作为硬件功能的描述,运用模块化设计方法分别设计了通用异步收发器(UART)的发送模块、接收模块和波特率发生器,并结合现场可编程门阵列(FPGA)的特点,实现了一个可移植的UART模块.该设计不仅实现了串行异步通信的主要功能,而且电路简单,工作稳定、可靠,可以将其灵活地嵌入到各个通信系统中.%The Verilog-HDL language was selected as the hardware function description method, and the modularity method was adopted to design the transmitter module, receiver module and baud rate generator of the universal asynchronous receiver-transmitter (UART) respectively. The whole structure of the UART module was programmable by using the field programmable gate array (FPGA). This design realized the main function of UART. The circuit of design is simple and works stably and credibly, and can be embedded into various communication systems flexibly.