基于动态电路的高速发送端设计

摘要

为了降低高速串行接口中发送端的延迟，在研究、分析现有发送端结构的基础上，提出了新的数据跨时钟域传输方法并在实际电路中得到实现。此方法可以大幅降低数据跨时钟域传输时用于异步FIFO的延迟。而且，使用动态电路对高速发送端并串转换电路进行了晶体管级的改进，放松了关键路径的时序要求，使发送端整体电路能运行在更高的频率下。发送端电路使用40 nm CMOS工艺实现，实际芯片测试数据表明，使用该电路的发送端可以稳定工作在13 Gb/s的速率下。%To lower the transmitter’ s delay of a high-speed serial interface, a new data transmission method under clock domain crossing was presented and realized in practical circuit design based on investigating and analyzing existing transmitter structures. This method can greatly reduce the delay for asynchronous FIFO during the data transmission under clock domain crossing. Moreover, the high-speed transmitter’ s serializing circuits were improved at transistor level by using dynamic circuits to relax critical paths’ timing requirement, so the transmitter’ s whole circuit can work under the higher frequency. The proposed transmitter’s circuit was manufactured with the 40nm CMOS technol-ogy, and the testing results demonstrate that the transmitter using the circuit can stably work at the rate of 13Gb/s.