无晶振快速锁定高精度锁相环设计

摘要

This paper studies the non-oscillator PPL structure , which can speedly lock the requiring frequency and is validated according the analog and digital module. The analog module is similar with classical architecture and the digital tracking frequency divider module searches system signal using unprecise initial clock of PLL, according the reference clock to adjust the output clock of the PLL. This structure can lock clock of PLL just using one host signal.%提出了一种无晶振锁相环结构,可快速锁定所需频率,并对模拟和数字模块分别进行了验证.模拟模块原理与经典结构相似,数字跟踪分频器模块利用初始时PLL不精确时钟搜索系统中的信号,根据搜索到的基准时钟调整PLL的输出,只需一个主机基准信号就可精确锁定所需的时钟频率.