用于锁相环快速锁定的鉴频鉴相器设计

摘要

针对鉴频鉴相器（PFD）的盲区现象对锁相环路的锁定速度的影响，设计了一种PFD结构，可以实现锁相环路的快速锁定。该结构在传统PFD的基础上，利用内部信号的逻辑关系进行逻辑控制，其输出特性呈现非线性；在输入相位差大于π时，抑制了复位脉冲的产生，避免了输入时钟边沿的丢失，有效消除了盲区，加快了锁相环的锁定速度。设计采用SMIC 0.18μm标准CMOS工艺，采用全定制设计方法对该PFD结构进行了设计、仿真分析和验证。结果表明，采用该PFD结构的锁相环，在400 MHz工作频率下锁定时间为2.95μs，锁定速度提高了34.27%。%Because of the effect on the lock speed of phase locked loop by the blind zone of phase frequency detector(PFD), the paper proposes a PFD circuit structure which can realise a quick lock acquisition of a phase locked loop. Based on the traditional PFD, the structure is designed with internal signal to control circuit logic, and its transfer characteristic is nonlinear. When the input phase error is lager thanπ, the reset pulse signal is suppressed, and the input clock edge is avoided missing. The blind zone is eliminated effectively to speed up the lock acquisition of a phase locked loop. Based on SMIC 0.18μm standard CMOS process, the PFD circuit structure is designed, simulated, analysed and veriifed in full custom design method. The simulation results indicate that the PLL with the proposed PFD circuit structure can accelerate lock acquisition by 34.27%, and its locking time is 2.95 μs working in the frequency of 400 MHz.