Engineering SiO2 Passivated Indium-Gallium-Zinc-Oxide TFTs for Improvement in Channel Control

摘要

The performance of Indium Gallium Zinc Oxide (IGZO) Thin-Film Transistors (TFTs) has improved significantly in recent years; however, device stability still remains a significant issue. In bottom-gate TFTs a difficult challenge is the lack of gate control on the back-channel region, resulting in distortion in ID - VGS characteristics. In this work a bottom-gate TFT process was established using SiO2 as a back-channel passivation layer. The process was modified with options to implement TG (TG) and Double-Gate (DG) configurations. TFTs were fabricated utilizing a SiO2 layer deposited shortly after the IGZO sputter process, followed by an oxidizing ambient anneal treatment. The process supports a low-defect IGZO interface, with TG and DG configurations demonstrating improvements in channel control compared to a traditional bottom-gate TFT. Electrical characteristics from each process treatment and gate configuration where then compared. A SPICE level 2 compatible IGZO TFT model was developed, with extracted parameter values providing a quantitative measure of device operation. Measured characteristics were also used to develop arerefined material and device model for TCAD simulation.