The effects of reactive ion etching on the electronic properties of silicon surfaces and power devices.

摘要

Trench technology for silicon power devices has advantages of high cell packing density and low on-resistance over planar silicon structures fabricated using the DMOS process. To obtain such trench (or UMOS) structures, dry etching, i.e., reactive ion etching (RIE), is employed in which gases attack the substrate surface with the combination of physical ion bombardment and chemical reaction. The anisotropic profile and good MOS characteristics are necessary for good device performance. However, it is known that reactive ion etching degrades the mobility and interface charge density of Si structures.; The electrical properties of the etched silicon surface depends upon the RIE etching conditions. In this study, a new Si etch process, based upon fluorine-containing plasmas, has been developed for satisfying the requirements of anisotropy and good electrical properties. The roughness and composition of the etched silicon surface have been examined via scanning electron microscopy (SEM), Auger electron spectroscopy (AES) and other surface analysis instruments. Trenches having nicely slope sidewalls and rounded bottom corners have been obtained. However, a undesirable surface roughness is created during the reactive ion etching step. Elements of carbon and oxygen detected by AES scans on the trench sidewalls were found to be responsible for the contamination and residue formation. Methods to remove such surface damage after the etching step have been explored. Electrical measurements of mobility and interface trap density of the etched silicon surface have also been studied by fabrication of a variety of device structures as a function of sidewall surface cleaning process. Furthermore, properties of oxide grown on the silicon surface, e.g., effective oxide charge density (N{dollar}sb{lcub}rm eff{rcub}){dollar} and breakdown strength, have been investigated.; Three new power UMOSFET structures have been proposed and fabricated utilizing the developed RIE process. When compared with the conventional UMOSFET structure, these devices have been found to have the lowest on-resistance ever reported.