Low-k materials as interlayer dielectrics in CMOS: The effects of deposition and processing on N-channel MOSFET's characteristics.

摘要

We report on comprehensive studies of the effects, on n-channel metal-oxide-silicon field-effect transistors (MOSFETs), of deposition and processing of low-k interlayer dielectrics (ILDs) in complementary MOS (CMOS). We have explored the ILD candidacy of fluorinated silicon oxide (FSO), fluorinated poly(erylene)ethers (FLARE), and divinylsiloxane-benzocyclobutane (BCB). We have observed that FLARE and BCB degradation by plasma exposures manifests itself as changes in the physical properties especially leakage current, which is observed to increase by several orders of magnitude. This degradation is proposed to result from bond scissioning, bond cross-linking and void formation processes which are promoted by ion bombardment, ultra-violet radiation, and plasma charging mechanisms associated with plasma exposures. The latter mechanism is suggested to be the dominant degradation mechanism in FLARE and BCB and is observed to contribute the largest share to MOSFET's damage from via etching of FLARE or BCB, as a second ILD, in a 0.35 and 0.5 mum channel length full flow CMOS process. The severity of this MOSFET damage is significantly reduced by the inclusion of a thin insulating Si3N4 layer underneath the ILD or annealing at 350°C in forming gas (94% N2 and 6% H2). In CMOS processes utilizing FSO as an ILD we have observed that fluorine interactions, coupled with plasma charging, adversely affects MOSFET's Fowler-Nordheim reliability via fluorine passivation/depassivation of bulk gate oxide and oxide/silicon interface defects. Overall, these results underscore the negative effects of ILD processing on MOSFET's characteristics and call for these effects to be reckoned with in making the choice of a suitable low-k ILD.