Wafer process of three-dimensional LSI chip stacking technology with copper interconnection through silicon wafer

摘要

The elemental and integral technologies of three-dimensional (3D) LSI chip stacking are described. Chip based stacking technology was developed. We have developed thorough electrode formation, wafer thinning, and chip stacking. The thorough electrode and micro bump dimensions are 10 μm square, 20 μm pitch. Chips are thinned up to 50 μm for high-density packaging. This technology overcomes the wiring delay of electronic systems. We summarize the wafer process of copper interconnection through silicon wafer.