This paper presents an approach to build electronic systems with very high chip count. Instead of packing the chips laterally as it is done in multichip-modules (MCMs), individual dies, blocks of dies and ultimately entire wafers are stacked on top of each other. Electrical interconnection is accomplished using plated through-hole contacts through the silicon substrate. Proper thermal management is obtained using dedicated heat distribution contacts, which can be fabricated by a judiciously designed mask layout and without additional processing effort. Thermally induced stress in the interconnections between the stacked layers is limited both by means of design and process variations.
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