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GaN growth on patterned silicon substrates. A thermo mechanical study on wafer bow reduction

机译:GaN在图案化硅基板上的生长。减少晶圆弯曲的热力学研究

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摘要

Residual stresses and strains are unavoidable after growing GaN epitaxial films on silicon wafers because of lattice and thermal expansion coefficient mismatch between them. Due to the high processing temperatures (>1000°C) and the difference in the coefficient of thermal expansion between the silicon substrate and the GaN layer, high tensile stresses are induced in the epitaxial layer when cooling from the growth temperature to room temperature. Besides possible dislocations and cracks in the GaN, these stresses have an effect also on the warpage of the wafer, making difficult or impossible the processing of subsequent steps. In this paper, we propose a solution to reduce, or even, eliminate the global wafer warpage over a wide range of temperatures. Deep patterned trenches are etched into the silicon substrate, eliminating the continuity of the GaN layer and isolating the stresses/strain into small islands. The effect of the geometry of these trenches on the mechanical behavior of the wafer has been studied by Finite Element Modeling (FEM). It has been found that by etching a trench of 80 µm and forming islands of 250 µm, the remaining warpage of the wafer is practically zero for the whole range of temperatures.
机译:在硅晶片上生长GaN外延膜后,由于它们之间的晶格和热膨胀系数不匹配,因此不可避免地会产生残余应力和应变。由于较高的处理温度(> 1000°C)和硅衬底与GaN层之间的热膨胀系数不同,当从生长温度冷却至室温时,在外延层中会引起高拉伸应力。除了GaN中可能的位错和裂纹外,这些应力还影响晶片的翘曲,从而使后续步骤的处理变得困难或不可能。在本文中,我们提出了一种解决方案,以减少甚至消除大范围温度下的整体晶圆翘曲。将深图案化的沟槽蚀刻到硅衬底中,从而消除了GaN层的连续性,并将应力/应变隔离为小岛。这些沟槽的几何形状对晶片机械性能的影响已通过有限元建模(FEM)进行了研究。已经发现,通过蚀刻80μm的沟槽并形成250μm的岛,晶片的剩余翘曲在整个温度范围内实际上为零。

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