Subquarter-micrometer p-channel MOSFET's with 80 nm S/D junctions

摘要

The p-channel MOS device technology is a key technology for CMOS VLSI's[1][2]. For realizing small gate length and high performance MOSFET's avoiding short channel effects, thin gate oxide and shallow source and drain (S/D) junctions are effective[3]. We have already reported high performance deep-submicrometer n-channel MOSFET's with ultra thin gate oxide[4], In this paper, we report high performance subquarter-micrometer n+ polysilicon gate p-channel MOSFET's with extremely shallow (80 nm) junctions and ultra thin (3.5 nm) gate oxide. Shallow p+n junctions were fabricated using pre-amorphization, low-energy BF2 ion implantation, and rapid thermal annealing. Shallow BF2 counter doping was performed to adjust the threshold voltage. Subquarter-micrometer gate patterns were defined by EB direct writing and ECR plasma etching. With these devices, a maximum transconductance of 280 mS/mm has been achieved.