A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit

摘要

High-speed low-power clock recovery circuits find wide application in high-performance communication systems [1]. This paper describes the design of a 2.5-Gb/sec 15-mW clock recovery circuit (CRC) fabricated in a 20-GHz 1-μm BiCMOS technology [2]. Employing a modified version of the 'quadricor-relator' architecture [3,4], the circuit extracts the clock from a non-return-to-zero (NRZ) data sequence using both phase and frequency detection.