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A Model of Silicon Nanocrystal Nucleation and Growth on SiO_2 by CVD

机译:CVD法在SiO_2上硅纳米晶成核和生长的模型

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Silicon nanocrystals can be used in non-volatile memory devices to reduce susceptibility to charge loss via tunnel oxide defects, allowing scaling to smaller sizes than possible with conventional Flash memory technology. In order to optimize device performance, it is desirable to maximize the nanocrystal density and surface coverage, while maintaining sufficient inter-crystallite separation to limit electron tunneling between adjacent crystallites. Ideally, crystallite densities in excess of 10~(12) cm~(-2) with relatively narrow particle size distributions must be obtained, posing a significant challenge for process development and control. In order to facilitate development of such a process, a rate-expression-based model has been developed for the nucleation and growth of silicon nanocrystals on SiO_2 in a CVD process. The model addresses the phenomena of nucleation, growth, and coalescence and includes the effects of exclusion zones surrounding the growing nuclei. The model uses a phenomenological expression to describe the nucleation rate and assumes that following nucleation, crystallite growth is dominated by gas-phase deposition processes, analogous to CVD of polycrystalline silicon. The model-predicted time-evolutions of crystallite densities and crystallite size distributions are consistent with experimental distributions as measured by Scanning Electron Microscopy (SEM). By coupling the model to a reactor-scale model of polysilicon CVD, it is possible to predict variations in the crystallite size distributions at various locations across a wafer as a function of reactor settings (temperature, pressure, flow rates, etc...). This in turn can be used for process control and optimization in order to ensure uniform deposition of nanocrystals in a large-scale manufacturing environment.
机译:硅纳米晶体可用于非易失性存储设备中,以降低通过隧道氧化物缺陷引起的电荷损失的敏感性,从而可将尺寸缩小到比传统闪存技术可能的尺寸小。为了优化器件性能,期望最大化纳米晶体密度和表面覆盖率,同时保持足够的微晶间分离以限制相邻微晶之间的电子隧穿。理想地,必须获得具有相对窄的粒度分布的超过10〜(12)cm〜(-2)的微晶密度,这对工艺开发和控制提出了重大挑战。为了促进这种工艺的发展,已经开发了基于速率表达的模型,用于在CVD工艺中在SiO_2上成核并生长硅纳米晶体。该模型解决了成核,生长和聚结现象,并包括了围绕生长核的排斥区的影响。该模型使用现象学表达式描述成核速率,并假设成核后,类似于多晶硅的CVD,微晶生长主要由气相沉积过程决定。模型预测的晶粒密度和晶粒尺寸分布的时间演化与通过扫描电子显微镜(SEM)测量的实验分布一致。通过将模型与多晶硅CVD的反应堆规模模型耦合,可以预测晶片上各个位置的微晶尺寸分布随反应堆设置(温度,压力,流速等)的变化。 。这又可用于过程控制和优化,以确保在大规模制造环境中均匀沉积纳米晶体。

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