Reliability aware yield improvement technique for nanotechnology based circuits

摘要

Lithography based IC manufacturing is approaching its physical limits in terms of feature size. In this scenario, nanotechnology based manufacturing, relying on self-assembly of nanotubes or nanowires, has been predicted as an alternative to CMOS technology. However, such processes are expected to have high defect density and therefore must be handled through effective defect tolerant techniques. In this paper, an innovative technique is proposed, which for a given circuit size utilizes different combinations of defect-free crossbars to build the desired circuit with improved yield. The goal of the proposed approach is to increase the number of defect free crossbars and the total yield, by connecting defect free subsets together. The reliability of the resulting circuits has been estimated, and the results have shown that the application of the proposed approach provides significant yield improvement, but also may decrease the reliability due to the growing number of interconnections. To overcome this drawback, a guideline to optimize the architecture by exploring an optimal trade-off between yield and reliability is proposed.