首页> 外文会议>Symposium on Gate Stack and Silicide Issues in Silicon Processing II, Apr 17-19, 2001, San Francisco, California >The Electrical Characteristics of the MOSCAP Structures with W/WN_x/poly Si_(1-x)Ge_x Gates Stack
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The Electrical Characteristics of the MOSCAP Structures with W/WN_x/poly Si_(1-x)Ge_x Gates Stack

机译:具有W / WN_x / poly Si_(1-x)Ge_x栅堆叠的MOSCAP结构的电学特性

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We investigated the electrical characteristics of the MOSCAP structures with W/WN_x/poly Si_(1-x)Ge_x gates stack using C-V and Ⅰ-Ⅴ. The low frequency C-V measurements demonstrated that the flat band voltage of the W/WN_x/poly Si_(0.4)Ge_(0.6) stack was lower than that of W/WN_x /poly Si_(0.2)Ge_(0.8) stack by 0.3V, and showed less gate-poly-depletion-effect than that of W/WN_x/poly- Si_(0.2)Ge_(0.8) gates due to the increase of dopant activation rate with the increase of Ge content in the poly Si_(1-x)Ge_x films. As Ge content in poly Si_(1-x)Ge_x increased, the leakage current level increased a little due to the increase of direct tunneling and Q_(BD) became higher due to the lower boron penetration.
机译:我们使用C-V和Ⅰ-Ⅴ研究了具有W / WN_x /多Si_(1-x)Ge_x栅堆叠的MOSCAP结构的电学特性。低频CV测量表明,W / WN_x / poly Si_(0.4)Ge_(0.6)堆栈的平带电压比W / WN_x / poly Si_(0.2)Ge_(0.8)堆栈的平带电压低0.3V,并显示出比W / WN_x / polySi_(0.2)Ge_(0.8)栅极更少的栅极多晶硅耗尽效应,这是因为随着多晶硅Si_(1-x)中Ge含量的增加,掺杂剂活化速率增加Ge_x电影。随着多晶硅Si_(1-x)Ge_x中Ge含量的增加,由于直接隧穿的增加,漏电流水平略有增加,并且由于较低的硼渗透率,Q_(BD)变高。

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