首页> 外文会议>Proceedings of the technical program, SMTA International 2009 >NO-FLOW UNDERFILL VOID NUCLEATION STUDY IN HIGH, STABLE YIELD, AND NEAR VOID-FREE ASSEMBLY PROCESS DEVELOPMENT
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NO-FLOW UNDERFILL VOID NUCLEATION STUDY IN HIGH, STABLE YIELD, AND NEAR VOID-FREE ASSEMBLY PROCESS DEVELOPMENT

机译:高,稳定产量和近无烟组件工艺开发中的无流量欠装空隙成核研究

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The advanced assembly process for a flip chip in packagern(FCIP) using no-flow underfill material presents challengesrnwith high I/O density (over 3000 I/O) and fine-pitch (down torn150 μm) interconnect applications because it has narrowedrnthe feasible assembly process of high electrical interconnectrnyield.rnIn spite of such challenges, a high (>99.99%), reliablern(sample size: 30) yield and nearly void-free (≈ 7.0%)rnassembly process has been achieved using commercial noflowrnunderfill material with a high I/O, fine pitch FCIP in ourrnpast research. The existing 7% void area could cause earlyrnfailures such as solders fatigue cracking or solder bridge inrnthermal reliability. Therefore, this study reviewed a classicalrnbubble nucleation theory to predict the conditions of voidsrnnucleation in assembly process. The heterogeneous nucleationrntheory found the critical point enabling stable voidsrnnucleation. From the result of nucleation theory, systematicrnexperiments were designed to eliminate underfill voidingrnusing parametric studies. The void formation studyrninvestigated the effect of critical temperature on underfillrnvoiding and solders wettability. Then, the study established arnhigh, stable yield and void-free assembly process combinedrnwith former study. The stability of the assembly process wasrnvalidated using a large scale of assemblies.rnThus, the classical bubble nucleation was explored to modelrnvoid nucleation in no-flow underfill process. Besides, thernsystematic studies presented in this paper allowed a high,rnstable yield and void-free flip chip assemblies with high I/O,rnfine pitch using no-flow underfill.
机译:使用无流动底部填充材料的倒装芯片封装(FCIP)的先进组装工艺提出了挑战,即高I / O密度(超过3000 I / O)和小间距(减小至150μm)互连应用,因为它缩小了可行的组装范围尽管存在这些挑战,但仍使用高流量的商用无底流填充材料实现了高(> 99.99%),可靠(样本量:30)和几乎无空隙(≈7.0%)的组装过程。 I / O,我们的研究中的小间距FCIP。现有的7%空隙面积可能会导致早期失效,例如焊料疲劳裂纹或焊料桥的热可靠性。因此,本研究回顾了经典的气泡成核理论,以预测组装过程中气泡成核的条件。异质成核理论发现了实现稳定的空核成核的临界点。从成核理论的结果出发,利用参数研究设计了系统的实验以消除底部填充空隙。孔隙形成的研究调查了临界温度对底部填充和焊料润湿性的影响。然后,本研究建立了与以前的研究相结合的高产量,稳定产量和无空隙的组装工艺。大规模装配验证了装配过程的稳定性。因此,探索了经典的气泡成核模型,以模拟无流动底部填充过程中的空隙成核。此外,本文提出的系统研究还允许采用无流动底部填充技术,以高I / O,细间距实现高产量,稳定的良率和无空隙的倒装芯片组件。

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