Stress measurements in large area array flip chip microprocessor chips

机译：大面积阵列倒装芯片微处理器芯片中的应力测量

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Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder in

机译：现代工作站和服务器中的微处理器包装通常由一个或多个大型倒装芯片管芯组成，它们安装在高性能陶瓷芯片载体上。最终组装配置具有将区域阵列焊料复杂地堆叠在其中的功能

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来源
《Power Semiconductor Devices & IC's, 2005 IEEE International Symposium on》|2008年|P.1462-1471|共10页
会议地点 Lake Buena Vista,FL,USA
作者
Roberts; J.C.; Rahim; M.K.; Suhling; J.C.; Jaeger; R.C.; Lall; P.; Ron Zhang; Jones; J.;
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flip-chip devices; microprocessor chips; stress measurement; ceramic LGA package; die stress effect; flip chip microprocessor chip; microprocessor packaging; piezoresistive sensor; silicon test chip;

机译：倒装芯片设备；微处理器芯片；压力测量；陶瓷LGA封装;压力效应倒装芯片微处理器芯片；微处理器包装；压阻传感器硅测试芯片;

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1. Dynamic flow measurements of capillary underfill through a bump array in flip chip package [J] . Seok Hwan Lee, Jaeyong Sung, Sarah Eunkyung Kim Microelectronics reliability . 2010,第12期

机译：通过倒装芯片封装中的凸块阵列动态测量毛细管底部填充的流量
2. Thermal stress analysis and design optimization of direct chip attach (DCA) and chip scale package (CSP) in flip chip technology [J] . D. S. Liu, C. Y. Ni, T. C. Tsay, Engineering Optimization . 2002,第6期

机译：倒装芯片技术中直接芯片连接（DCA）和芯片级封装（CSP）的热应力分析和设计优化
3. Test chip and substrate design for flip chip microelectronic package thermal measurements [J] . Goh TJ, Chiu CP, Seetharamu KN, Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe . 2006,第2期

机译：用于倒装芯片微电子封装热测量的测试芯片和基板设计
4. Stress measurements in large area array flip chip microprocessor chips [C] . Roberts J.C., Rahim M.K., Suhling J.C., Electronic Components and Technology Conference . 2008

机译：大面积阵列倒装芯片微处理器芯片压力测量
5. Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic lead-tin and lead-free solders. [D] . Huang, Xingjia. 2003

机译：用共晶铅锡和无铅焊料对塑料球栅阵列，芯片规模和倒装芯片封装的焊球剪切强度进行调查和分析。
6. Barriers-on-chips: Measurement of barrier function of tissues in organs-on-chips [O] . Yusuf B. Arık, Marinke W. van der Helm, Mathieu Odijk, 2018

机译：片上屏障：片上器官中组织屏障功能的测量
7. Measurement of Local Two Dimensional Stress Distribution in a Flip Chip Structure by Using Strain Sensor Chips with 2-.MU.m Long Piezoresistance Gauges [O] . Takuya Sasaki, Nobuki Ueta, Hideo Miura 2009

机译：使用应变传感器芯片用2-μm长压电仪测量倒装芯片结构中局部二维应力分布的测量
8. Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method [R] . Peterson, D. W., Sweet, J. N., Burchett, S. N., 1996

机译：倒装芯片组装和底部填充应力;用aTC4.1装配测试芯片测量并用有限元法分析

Stress measurements in large area array flip chip microprocessor chips

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