Modeling FinFET metal gate stack resistance for 14nm node and beyond

摘要

A FinFET high-k replacement metal gate stack resistance model is proposed. Introduction of non-negligible contact resistance existing in boundaries between metal layers achieves a good model accuracy which is validated by FEM-based simulation results in 14nm and 10nm technology nodes. Impact of the contact resistance on digital and analog circuit is investigated, resulting in 20% degradation of analog speed by 5 Ω·μm contact resistance. The derived gate resistance model is applicable to further downscaled FinFET technology.