ASPIRE INVENT ACHIEVE: ESD Considerations on 3D Stacked Integrated Circuits using Through-Silicon-Via (TSV) and Micro-Bumps - (PPT)

摘要

There is no significant influence of TSV mechanical strain on TLP and vfTLP IV. characteristics of ESD protection devices in planar and bulk FinFET processes. The ESD protection devices can be safely implemented inside the KOZ. S. Chen EOSESD2012 to be published.