On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

摘要

This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient performance of TSVs. In addition, Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ring-based oscillator test structure is proposed and simulated based on a high performance fully tunable electrical circuit pi-model where a single and coupled TSVs with ground-signal-ground (GSG) and ground-signal-signal-ground (GSSG) 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. Simulation results are presented using the Keysight/Agilent Advance Design System (ADS) and a standard 0.25 μm CMOS process.