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DEVICE LEVEL 3D INTEGRATION TECHNOLOGIES FOR HIGH PERFORMANCE/RELIABILITY MODULES

机译:用于高性能/可靠性模块的设备级别3D集成技术

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As electronics continue towards higher performance and smaller form factors, interest in 3D die level integration has moved to the forefront. While current 3D packaging solutions, involving a combination of high density circuit boards with stacked ICs using wire bond interconnect, can satisfy some of the performance and form factor requirements, 3D die level integration is proving to be the solution of choice for many mission critical, applications. The key features of 3D die level integration are very high levels of integration, very small form factor packages (often chip scale in size), very low profile packages, low weight packages, and improved digital and RF performance. This paper will briefly review 3D integration technologies, present implementation strategies for 3D die level integration packaging, and present examples of 3D die level integrated packaging solutions.
机译:随着电子产品的性能越来越高,形状较小的因素,对3D模具级集成的兴趣已经迁移到最前沿。虽然当前3D包装解决方案,涉及使用带叠层IC的高密度电路板的组合,但可以满足一些性能和形状因子要求,3D模具级集成被证明是许多任务关键任务的选择解决方案,应用程序。 3D模具级集成的关键特征是非常高的集成度,非常小的外形封装(通常芯片规模尺寸),非常低的型材包,低重量封装,以及改进的数字和RF性能。本文将简要介绍3D集成技术,目前的3D模具集成包装的实施策略,以及3D模级集成包装解决方案的实例。

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