1.8 V CMOS Low Noise CPPLL Design

摘要

This paper describes a design of a low noise Charge Pump PLL. The design utilizes a top - down methodology to determine system parameters. Using the behavioral simulation, the performance of the PLL system is verified. The PLL circuit design is based on 0.18um CMOS process and its supply voltage is 1.8V. The PLL has an input clock frequency of 12MHz and an output clock frequency of 480MHz with eight phases. According to the measurement the cycle-to-cycle jitter of the output clock at 480Mhz is only 60ps peak-to-peak, the long term jitter is 90ps. Moreover, the maximum lock time is about 6us and the maximum frequency overshot is about 13%, power dissipation is 7.2mW. The testing results prove precision of behavioral simulation.