Some design techniques for low power low noise CMOS amplifier with noise optimization for wireless application in GHz frequencies.

摘要

In recent years, there have been growing demands for bandwidth, for both voice and data communications. The Radio Frequency integrated circuit (RFIC) and wireless market has suddenly expanded to unimaginable dimensions.; Historically, RFIC's are implemented in III-V compounded semiconductors or in bipolar technologies. The DSP circuits, on the other hand, require small feature sizes to guarantee high speed of operation with low power consumption, hence the use of Complementary Metal-Oxide Semiconductor (CMOS) technologies.; The challenges are not only to design RF transceivers in CMOS processes, but also to establish design methodologies for their building blocks. This thesis is concerned with one of the main building blocks, namely the Low Noise Amplifier (LNA). Several low Voltage LNA's have been successfully implemented in a standard 0.18 um CMOS technology, operating in the 2.4-5 GHz frequency band. A new and very simple low voltage common source-common gate topology is suggested for low power consumption. The simulated results show the proposed topology is to be the choice in today's low power design with good performance in all aspects, when compared to other topologies. (Abstract shortened by UMI.)