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Design of 3.1-6.0 GHz CMOS Ultra-Wideband Low Noise Amplifier with Forward Body Bias Technique For Wireless Applications

机译:设计3.1-6.0 GHz CMOS超宽带低噪声放大器,具有用于无线应用的前体偏置技术

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This paper presents a design of 3.1-6.0 GHz CMOS ultra-wideband low noise amplifier (UWB LNA) with forward body bias technique for wireless applications. The UWB LNA is designed and simulated using 0.13-μm technology in Cadence software. The proposed UWB LNA consists of two stage common-source (CS) amplifiers with a forward body bias technique. A source degenerated inductor is used at the first stage to achieve a wideband input matching and high linearity. At the second stage, a shunt-peaking inductor is employed to enhance gain at higher frequency. The simulation results indicate that the proposed UWB LNA achieves a power gain (S21) of 10 dB, an input return loss (S11) is less than -5 dB, a minimum noise figure (NF) of 8.5 dB in the frequency range of 3.1- 6.0 GHz with power dissipation of 17.2 mW. The linearity analysis shows a 1 dB compression point (PldB) of-9 dBm and the third-order intermodulation intercept points (IIP3) of 4 dBm are achieved. The proposed UWB LNA's layout is 0.68 mm~2.
机译:本文介绍了3.1-6.0GHz CMOS超宽带低噪声放大器(UWB LNA)的设计,具有前置的无线应用的身体偏置技术。 UWB LNA在Cadence软件中使用0.13-μm技术设计和模拟。所提出的UWB LNA由两个阶段公共源(CS)放大器组成,具有前体偏置技术。在第一阶段使用源退化电感器以实现宽带输入匹配和高线性度。在第二阶段,采用分流峰值电感器来提高较高频率的增益。仿真结果表明,所提出的UWB LNA实现了10dB的功率增益(S21),输入返回损耗(S11)小于-5dB,频率范围为3.1的最小噪声系数(NF)为8.5 dB - 6.0 GHz,功耗为17.2 MW。线性分析示出了1dB压缩点(PLDB)的-9 dBm,并且实现了4dBm的三阶互调拦截点(IIP3)。所提出的UWB LNA的布局为0.68mm〜2。

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