A successful implementation of dual damascene architecture to copper TSV for 3D high density applications

摘要

Dual damascene integration was applied to High Density Through Silicon Vias in order to provide a low-cost TSV process. The architecture was developed for 3μm-width and 20μm-height vias to fit electrical and morphological requirements. Electrical results show the manufacturability of the process (>95% yield). Using LETI internal cost model, we estimate a cost reduction of 23% compared to single damascene Redistribution Layer.